When the output buffer of an integrated circuit switches the voltage on the output node in order to change a given logic level, an inductive extra voltage is generated on the power supply lines. This extra voltage is determined by the product of the parasitic inductance L of the line (which is typically comprised between a few nH and over 10 nH) and the time derivative of the current I.sub.out supplied by the buffer in order to rapidly charge or discharge the load capacitor. This extra voltage (often termed "switching noise") can reach such values as to compromise the correct operation of the integrated circuit to which the buffer belongs. The problem is more serious in the case where several nodes in the same integrated circuit have the same driving requirements in terms of speed and capacitive load (for example the data outputs in a memory circuit), and there is the potential for simultaneous logic switching on a plurality of these nodes.
FIG. 1 shows a known output circuit. The block indicated schematically by the broken line, contains a P-channel pull-up transistor MU' and an N-channel pull-down transistor MD' which have their sources connected to power supply lines V.sub.DDI, and V.sub.SSI, respectively. The output circuit includes a common node which is connected to the output node OUT to be switched.
The internal power supply lines are connected to respective external power supplies V.sub.DD and V.sub.SS through parasitic inductances L.sub.VDD and L.sub.VSS. The transistors MU' and MD' are controlled by respective UPN and DW gate signals which can assume a low level (or "0"), typically equal to 0 V, or a high level (or "1"), typically 5 V. Each of the two signals shifts from one level to the other very rapidly, so as to have a low output voltage switching time (hereinafter more simply termed "switching time").
The two signals UPN and DW often coincide, but can be different in order to switch off both transistors. Switching off both transistors places the output node OUT in a high-impedance state ("tristate" operation). Additionally, this state minimizes the flow of direct current between V.sub.DD, and V.sub.SS, by means of appropriate timings of the signals.
In order to switch the output voltage V.sub.OUT, for example from high to low, the two signals UPN and DW are both raised high. The transistor MU' switches off, and the transistor MD' starts to conduct, with a consequent sudden variation in the current which it delivers.
Current flows in the parasitic inductance L.sub.VSS. This current flow creates switching noise. If the delivered current is reduced in order to reduce switching noise, the consequence is an undesirable increase in switching time.
A similar problem occurs when the opposite switching of the output voltage is performed.
Various proposals have been offered to solve the problem of switching noise without incurring excessive penalties in switching time. For example, the European patent application No. 284,357, filed on Mar. 22, 1988 in the name of S. Oshima et al., entitled "Semiconductor Integrated Circuit Having a Data Output Buffer Circuit", proposes to separate the pads and the metal lines for the power supply of the internal circuitry of the device and for the power supply of the buffer. These separated pads and metal lines would reduce the noise induced on the power supply lines of the internal circuitry of the integrated circuit during the switchings of the output voltage by reducing the greatest contribution to the parasitic inductance of a line; that is, by reducing the inductance given by the wire which connects the pad and the lead (termed "bonding wire"). This refinement may be useful but it is not a complete or substantially complete solution to the problem.
Another known method for reducing switching noise consists of introducing appropriate offsets among the switchings of different output nodes in order to prevent the adding of current variations related to different nodes. This solution is most effective in the case of simultaneous switching of a plurality of nodes.
Another method consists in replacing the pull-up and pull-down transistors of the buffer with a plurality of transistors in parallel, and by appropriately offsetting the switchings of the various transistors of an individual buffer (see D.T. Wong et al., "An 11-ns 8K.times.18 CMOS Static RAM with 0.5-.mu.m Devices", IEEE J. Solid-State Circuits, vol. SC-23, No. 5, Oct. 1988, pages 1095-1103). These methods have the disadvantages of depending heavily on the manufacturing process and require in any case accurate experimental characterization.
Methods for preloading the output node at a level intermediate between V.sub.SS and V.sub.DD before performing actual switching are also well-known in the art (see for example T. Wada et al., "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", IEEE J. Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pages 727-732, or H. Okuyama et al., "A 7-ns 32K=8 CMOS SRAM", IEEE J. Solid-State Circuits, vol. SC-23, No. 5, Oct. 1988, pages 1054-1059). In this manner, the voltage change on the node when actual switching occurs is obviously reduced. Additionally, this method reduces the time variation of the associated current. This method is useful in those cases in which there is a dead time between the request for a new datum and its reading, for example in memory circuits.
Similarly, a method is described in the European patent application No. 271,331, filed on Dec. 9, 1987 in the name of S. Takayasu, entitled "Semiconductor Integrated Circuit". In this method, the output node is preloaded only when the initial output level is "1" and is also performed when an input value of an electronic circuit appears to be a high level (for example 2.5 V). The output node is not preloaded if the initial output level is "0" because this situation is considered non-critical.
All of the above described preloading methods reduce the extent of the problem but do not eliminate the problem. Furthermore, some of these methods may only be used with some types of device, such as memories.
Another method in widespread use for reducing switching noise consists of controlling the driving of the pull-up and pull-down transistors. The driving of the transistors is controlled such that the peak value of the time derivative dI.sub.out /dt of the current I.sub.out supplied by said transistors is as low as possible compatibly with the switching speed requirements. For example, it has been proposed to drive the gate electrodes of the output pull-up and pull-down transistors through a resistor which is arranged in series to said electrodes or to the positive and/or negative power supply of the logic gates which drive said electrodes. These resistors slow down, with a preset time constant, the rise and drop of the voltage applied to said electrodes; and, thus reduce the sudden variation in the current delivered by the buffer (see for example European patent application No. 251,910, filed on Jun. 25, 1987 in the name of M. Naganuma, entitled "CMOS Output Buffer Circuit"; or K.L. Wang et al., "A 21-ns 32K=8 CMOS Static RAM with a Selectively Pumped p-Well Array", IEEE J. Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pages 704-711).
In other cases it has been proposed to perform this control of the driving voltages by means of active networks (see for example W.C.H. Gubbels et al., "A 40-ns/1OOpF Low-Power Full-CMOS 256K (32K.times.8) SRAM", IEEE J. Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pages 741-747; or S.T. Chu et al., "A 25-ns Low-Power Full-CMOS 1-Mbit (128K.times.8) SRAM", IEEE J. Solid-State Circuits, vol. SC-23, No. 5, Oct. 1988, pages 1078-1084).
However, the above mentioned methods for controlling the driving of the transistors of the buffer have led to solutions which predominantly depend on the manufacturing process. Dependence on the manufacturing process necessarily leads to the need to comply with rather wide design margins. For instance, a design margin might include the setting for the maximum peak value of the time derivative of the output current. Compliance with these wide design margins result in the reduction of the switching speed of the output buffer. Thus, there is a need for a fast driving current generator which minimizes switching noise at high switching speeds even with heavy capacitive loads.